The invention relates to a ROM with four-phase dynamic circuits and, more particularly, to a ROM with four-phase dynamic circuits constructed by availing a four-phase operation concept fused with skill of pseudo-domino circuits and HS-PDCMOS dynamic circuits, which may be applied in high speed read only memory (HS ROM), high density read only memory (HD ROM) and embedded read only memory (embedded ROM). Moreover, owing that it's an improvement in circuit construction method, the invention may be applied in electrically-controlled read only memory (For example,EPROM,E.sup.2 PROM,Flash ROM,etc.).
A decent construction and a memory cell structure of a ROM circuit are usually designed to meet product requirements in electrical characteristics and cost. The basic logic style of a memory cell array may be classified as of NAND/AOI [4] [12-17] [19-20] [21-28] and NOR [5-11], wherein the latter is commonly applied for a high speed ROM, while the former for a middle or low speed ROM at high capacity respectively.
The chip area is a key factor concerning cost of chip fabrication; the larger the chip area, the higher the cost. So as to minimize the area, the memory cell array of a NAND/AOI logic style is normally applied for designing a ROM. However, on the contrary, owing to a plurality of cascade N type transistors used in the memory cell array of the NAND/AOI logic style, the operation speed of the ROM is bound to be slowed down.
FIG. 1 is a block diagram showing a reading process of either a masked or an electrical ROM. In general, memory cells are arranged in an array (B), and during a reading process, an address bus sends address to input terminal of an address buffer (D). The output from the buffer (D) are splitted into: m lines feeding a row decoder (A) to provide row address, n lines feeding a column decoder (C) to provide column address. The selected data are then sent to a data bus via an output buffer (E). Besides, a clock signal is employed to assure synchronous action of the ROM to the system circuit.
Skill of dynamic circuits is used frequently to improve circuit performance for minimizing circuit area and increasing operation speed in a CMOS circuit design. FIG. 2A is a schematic view of partial circuit (critical path shown only) of a ROM [14] using conventional MOS dynamic circuits and logic style of AOI memory cell array (Including a row decoder 11, memory cell array 12, column decoder 14 and output latch 13). Assuming the CMOS fabricating technology is applied to design an AOI-type mask ROM, then, this design shall require enhancement NMOS' depletion NMOS' and/or enhancement PMOS transistors, wherein the depletion NMOS transistor is only used in the memory cell array for coding purpose. In the case of designing an E.sup.2 PROM, the related E.sup.2 PROM elements shall be utilized in the memory cell array, namely, the NMOS transistors have to be replaced by those for E.sup.2 PROM, which are programmable to create a high or low device threshold voltage (Vt). In such kind of conventional dynamic circuits in a ROM and due to domino effect [2], there is only one clock signal line CK required for the integral circuit, as shown by upper waveform in FIG. 2B. When CK=0 (logic low), the circuit is proceeding precharge [2], while CK=1 (logic high), the circuit is to evaluate in a sequential order of row/column decoder-memory cell array-output latch. Under normal conditions, time required for evaluation is always longer than precharge. In other words, time of evaluation limits the operation speed of a ROM. If we design a clock with shorter precharge time, the performance of the ROM could be improved. The lower waveform in FIG. 2B indicates a clock with shorter precharge time.
In an AOI-type mask ROM, a plurality of cascade N type transistors are arranged in the memory cell array as shown in FIG. 2A, which is the main factor delaying evaluation of a ROM. If shortcomings of this portion could be improved, the operation of the integral circuit would be speeded up undoubtedly.